As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth and latency requirements are met for optimal component operation. Furthermore, different market segments need different interconnect architectures to suit the market's needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings.
High speed serial interconnect links are used for in system communications between processors, disks, external interfaces, and numerous other units. These links may need to be coherent, e.g., ensuring identical memory contents in different locations. The serial interconnect links can include links between processor cores on a single die, for example, an intra-device interconnect (IDI). This provides a high-speed, low latency connection, but is not generally suitable for longer connection lengths.
Communications between chips that may be located on a single board or backplane may use a more suitable interconnection, such as the quick-path interconnect (QPI) from Intel, the ultra-path interconnect (UPI) from Intel, or similar protocols. These interconnections may be more complex than IDI, but provide fast communications between proximate devices. The proximate location of the devices for the IDI and QPI allow a shared clock signal, which can lower complexity and latency, and allow hardware synchronization, for example, through a drift buffer.
Longer distance communications, for example, across multiple boards or even cables between device cabinets, may use the peripheral component interconnect express (PCIe) protocol, which provides stable communications, and allows the use of extension devices. This communications protocol does not use a shared clock signal, but uses a protocol mechanism to compensate for the timing differences that may be present. This allows synchronization of data through a buffer termed an elastic buffer. Further, the PCIe standard uses an error encoding technique that allows the recognition and correction of errors, such as 8b/10b or 128b/130b. These encoding techniques increase the accuracy of the transmission, but increase latency and decrease total throughput.
Integrated circuits often have the protocol stacks for these communications designed into the chip itself. There may be a certain number of each type of interconnect protocol on each chip. However, the chips may not include a sufficient number of one of the types of interface, which may lead to expensive redesigns prior to fabrication.